A SystemVerilog language server based on the Slang library.
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Systemverilog GitHub Repositories (2026) · Open Source Tools
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5 matching projects · updated Nov 13, 2026
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SystemVerilog compiler and language services
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Verilog/SystemVerilog support for VS Code
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Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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