Digital logic design tool and simulator
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Digital logic design tool and simulator
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
A SystemVerilog language server based on the Slang library.
SystemVerilog compiler and language services
Ruby interface to IEEE 1364-2005 Verilog VPI