Verilog GitHub Repositories (2026) · Open Source Tools

Digital logic design tool and simulator

SystemVerilog compiler and language services

XLS: Accelerated HW Synthesis

cocotb: Python-based chip (RTL) verification

Modular hardware build system

Verilog/SystemVerilog support for VS Code

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

Ruby interface to IEEE 1364-2005 Verilog VPI

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX