jeras/red-pitaya-notes
My notes on the Red Pitaya Open Source Instrument
A set of small Verilog projects, to simulate and implement on FPGA development boards
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My notes on the Red Pitaya Open Source Instrument
Automatically exported from code.google.com/p/axi-bfm
RISC processor 8bit (AVR ISA), RTL based on 'navre'
brute-force rule equivalence search