jeras/CA-equivalence
brute-force rule equivalence search
RISC processor 8bit (AVR ISA), RTL based on 'navre'
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brute-force rule equivalence search
RISC-V assembler/dis-assembler written in SystemVerilog
improvized rv32_1stage translation from Chisel to SystemVerilog
Displaying 2D CA (quad) preimage network