jeras/three.js
Displaying 2D CA (quad) preimage network
Developer Profile
jeras
Discovered public repositories for jeras in the GitHub catalog.
jeras/waveform_examples
A set of examples to be used by GTKWave for experimenting with SystemVerilog data types
jeras/verilog_coding_style
Verilog coding style examples
jeras/butterflylogic
Public repository.
jeras/office
LibreOffice templates
jeras/fpga_synthesys_issues
Debugging FPGA synthesis issues, article and examples
jeras/jeras.github.io
personal "Rattus Pubis" webpage
jeras/sockit_i2c
I2C master/slave RTL and bench model code
jeras/zbus
symmetric low resource bus
jeras/sigrok
sigrok
jeras/sigrok-dump
Example sigrok dumps
jeras/ivtest
Regression test suite for Icarus Verilog.
jeras/iverilog
Icarus Verilog
jeras/SystemVerilog-tests
Tests for a set of SystemVerilog features over a set of simulation and synthesis tools.
jeras/sockit_cdc
clock domain crossing FIFO
jeras/Terasic_DE1
Demo designs for the Terasic DE1 board
jeras/ecs8
projects related to the ECS8 board
jeras/sockit_spi
SocKit SPI (3-wire, dual, quad) master
jeras/sockit_owm
SocKit 1-wire (onewire) master
jeras/fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
jeras/soc-kit
System on Chip toolkit (Verilog 2001)