jeras/rp8
RISC processor 8bit (AVR ISA), RTL based on 'navre'
Public repository discovered through GitHub real-time crawl.
This repository is cataloged as part of our automated global GitHub synchronization. Full telemetry, velocity snapshots, and code summaries are scheduled for continuous enrichment.
RISC processor 8bit (AVR ISA), RTL based on 'navre'
brute-force rule equivalence search
RISC-V assembler/dis-assembler written in SystemVerilog
improvized rv32_1stage translation from Chisel to SystemVerilog