funningboy/xbus
an easy bus verification example based on UVM/SV framework
Public GitHub Catalog
Discovered Sep 26, 2026
funningboy / PyVerilog
Python-based Verilog Parser (currently Netlist only)
About this discovery
This repository is cataloged as part of our automated global GitHub synchronization. Full telemetry, velocity snapshots, and code summaries are scheduled for continuous enrichment.
#8311440GitHub System ID
funningboyOrganization / User
PublicVisibility
ActiveCatalog Status
More from funningboy
funningboy/msp430_cc3000_smartconfig
Connect to the cloud using TI's CC3000 WiFi & Exosite's services
funningboy/carCV
carCV
funningboy/Adafruit_CC3000_Library
Library code for Adafruit's CC3000 WiFi breakouts &c