funningboy/gevent-zeromq
pyzeromq gevent compat. lib
Discovered public repositories for funningboy in the GitHub catalog.
pyzeromq gevent compat. lib
Public repository.
Android Video Chat Application with ZeroMQ an Node.js
Bitcoin mining with the X6500 FPGA Miner
Public repository.
NumPy aware dynamic Python compiler using LLVM
Example OpenRISC backend
build up a co-sim verification env via openCV and myHDL
QUANTITATIVE ECONOMICS, by John Stachurski and Thomas J. Sargent
UVM/systemverilog/verilog/python VIM IDE
TLMu - Transaction Level eMulator
example big data
soc regression flow by jenkins
demo how to use HW/SW co-verification
A Bitcoin miner for the Zynq chip utilizing the Zedboard.
The Shang high-level synthesis framework
An FPGA-Based Embedded System to Autonomously Play Music Video Games
A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL).
uvm AXI BFM(bus functional model)
Open Component Portability Infrastructure
Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!
The official Linux kernel from Xilinx
Release history of Verilog-Pli
Public repository.
Jenkins Continuous Integration Server
useful scripts
python vpi interface for systemverilog.
System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
台灣上市股票價格擷取(Fetch TWSE stock data)含即時盤、台灣時間轉換、開休市判斷。
git clone of http://code.google.com/p/axi-bfm/
PyZMQ: Python bindings for zeromq
Python wrapper for TA-Lib (http://ta-lib.org/).
Python financial trading, research and backtesting library
OpenCV examples in Python
Scrapy, a fast high-level screen scraping and web crawling framework for Python.
OpenCV GitHub Mirror
systemc-2.3.0
Connecting SystemC with SystemVerilog
Icarus Verilog
matplotlib: plotting with Python
This is a github clone of the offical pygame repo, because let's face it, bitbucket sucks ass.
The Open Source Framework for Machine Vision
Python-based Verilog Parser (currently Netlist only)
example code for MyHDL project
Code for High Performance Computing tutorial for EuroPython 2011
vbench: A tool for benchmarking your code through time, for showing performance improvement or regressions
Flexible and powerful data analysis / manipulation library for Python, providing labeled data structures similar to R data.frame objects, statistical functions, and much more
Structural Checking of Voltage-Island and Power Gating Low-Power Logic Design
DFG synthesis
Pattern Generation for Logic BIST