High-speed simulation model for Network-on-Chip with Link Aggregation written in SystemC (C++). Not synthesizable. Allows to define traffic pattern for a given application, configure number of physical links in each trunk and perform optimization of NoC's hardware costs for a given traffic pattern
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Network-on-Chip (NoC) with Link Aggregation (LAG), modified for synthesis in Quartus II. Repo contains LAG.tcl that creates and configures Quartus II project of the NoC with LAG. In addition, gate level model of the NoC with LAG can be created and than simulated in ModelSim.
Router for Network-on-Chip (NoC) with Virtual Channels (VC) from Netmaker library, modified for synthesis in Quartus II
Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Implements uniform-random spatial distribution of traffic and equal number of physical links in each trunk. Intended for simulation in ModelSim.
Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Allows to define spatial distribution of traffic for a given application and choose number of physical links in each trunk. Intended for simulation in ModelSim.