gauravtewari/vhdl-designs
Practice files for VHDL Digital Design
Developer Profile
gauravtewari
Discovered public repositories for gauravtewari in the GitHub catalog.
gauravtewari/python-to-verilog
Generate a Verilog Source file and testbench file for a given Moore FSM
gauravtewari/netlist
To build data structures for netlist description and to calculate fan outs and fan ins
gauravtewari/sta
Static Timing Analysis Assignment for EE5301 Proj 1b