# y3nr1ng/MIPS

> Verilog behavioral modeling of a 5-stage pipeline MIPS processor with builtin L1 cache.

- **Canonical URL**: https://githubrepo.cloud/repo/y3nr1ng/MIPS
- **GitHub Repository**: https://github.com/y3nr1ng/MIPS
- **Maintainer / Creator**: https://github.com/y3nr1ng
- **Discovered On**: Nov 1, 2026

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