# vlad-ivanov-name/verilog-zeroall

> Resets all register to zero in a Verilog design

- **Canonical URL**: https://githubrepo.cloud/repo/vlad-ivanov-name/verilog-zeroall
- **GitHub Repository**: https://github.com/vlad-ivanov-name/verilog-zeroall
- **Maintainer / Creator**: https://github.com/vlad-ivanov-name
- **Discovered On**: Nov 2, 2026

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