# rbarzic/edn_2015_01_12

> A Verilog implementation of the gating circuit described in EDN : http://www.edn.com/design/systems-design/4438302/Circuit-gates-pulse-train-without-truncating

- **Canonical URL**: https://githubrepo.cloud/repo/rbarzic/edn_2015_01_12
- **GitHub Repository**: https://github.com/rbarzic/edn_2015_01_12
- **Maintainer / Creator**: https://github.com/rbarzic
- **Discovered On**: Oct 5, 2026

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