quicky2000/top_test_sharp_screen
VHDL design to test Sharp LCD screen with Papilio card
SODA module to dump all data created/modified/deleted by a user
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VHDL design to test Sharp LCD screen with Papilio card
VHDL register IP
VHDL IP allowing to draw a 640*480 black and white picture stored in block RAM
VHDL IP that generate an output indicating falling edge of input