oetr/AoW
Algorithm of the week
Public GitHub Catalog
Discovered Oct 3, 2026
oetr / asip-dsl
A domain-specific language for making ASIPs that will be converted into VHDL code for subsequently running them on FPGAs
About this discovery
This repository is cataloged as part of our automated global GitHub synchronization. Full telemetry, velocity snapshots, and code summaries are scheduled for continuous enrichment.
#28184782GitHub System ID
oetrOrganization / User
PublicVisibility
ActiveCatalog Status
More from oetr
oetr/FPGA-I2C-Minion
A simple I2C minion in VHDL
oetr/racket-processor
Racket VM on FPGAs
oetr/gng
Growing neural gas in Racket