maltanar/seyrek
A framework for generating semiring-based sparse graph accelerators for FPGAs
A sandbox for experimenting with the Sodor educational cores from UC Berkeley. See https://github.com/ucb-bar/riscv-sodor
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A framework for generating semiring-based sparse graph accelerators for FPGAs
Chisel components for FPGA projects
Chisel wrappers and examples for Convey's Wolverine FPGA accelerators
Automatically exported from code.google.com/p/wirelesssquirrel