damnsavage/interconnect
interconnect rtl
Public GitHub Catalog
Discovered Sep 28, 2026
damnsavage / analog_models
Wreal models of analog circuit components (verilog ams)
About this discovery
This repository is cataloged as part of our automated global GitHub synchronization. Full telemetry, velocity snapshots, and code summaries are scheduled for continuous enrichment.
#13499762GitHub System ID
damnsavageOrganization / User
PublicVisibility
ActiveCatalog Status
More from damnsavage
damnsavage/e_to_c_translator
specman e to c translation