# alok-upadhyay/MIPS-in-Verilog

> An implementation of MIPS single cycle datapath in Verilog. 

- **Canonical URL**: https://githubrepo.cloud/repo/alok-upadhyay/MIPS-in-Verilog
- **GitHub Repository**: https://github.com/alok-upadhyay/MIPS-in-Verilog
- **Maintainer / Creator**: https://github.com/alok-upadhyay
- **Discovered On**: Sep 25, 2026

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