Nepomuk/jdrs
Jülich Digital Readout System for testing ASICs under development.
A simple module in VHDL which controls the LCD (S162D)on the ML605 development board (Virtex6) from Xilinx.
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Jülich Digital Readout System for testing ASICs under development.
Some tools to use with the pyLoad download manager
Small Python script to repeatedly check for a valid internet connection.
The configuration of my Sublime Text 3 editor.