# KorotkiyEugene/LAG_sv_sim_predef_traffic_predef_links

> Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Allows to define spatial distribution of traffic for a given application and choose number of physical links in each trunk. Intended for simulation in ModelSim.

- **Canonical URL**: https://githubrepo.cloud/repo/KorotkiyEugene/LAG_sv_sim_predef_traffic_predef_links
- **GitHub Repository**: https://github.com/KorotkiyEugene/LAG_sv_sim_predef_traffic_predef_links
- **Maintainer / Creator**: https://github.com/KorotkiyEugene
- **Discovered On**: Sep 29, 2026

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