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Catalog / BenjaminSmith-cpe / cpe142TermProject
Public GitHub Catalog Discovered Oct 3, 2026

BenjaminSmith-cpe / cpe142TermProject

Three stage pipelined MIPS CPU in System Verilog

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This repository is cataloged as part of our automated global GitHub synchronization. Full telemetry, velocity snapshots, and code summaries are scheduled for continuous enrichment.

#27011232GitHub System ID
BenjaminSmith-cpeOrganization / User
PublicVisibility
ActiveCatalog Status

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BenjaminSmith-cpe/Vic-1

A verilog implementation of Tennenbaum's MIC-1 cpu in his textbook Advanced Computer Organization.

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