chiggs/reduct
Reduce a toolchain to the bare minimum set of files required
Developer Profile
chiggs
Discovered public repositories for chiggs in the GitHub catalog.
chiggs/travis_experiment
Public repository.
chiggs/comp.lang.verilog
Code samples etc from alt.lang.verilog
chiggs/sv_benchmarking
Some random benchmarks of SV and Python
chiggs/UVM
Mirror of the Universal Verification Methodology from sourceforge
chiggs/alt.hdl
Exploration of alternative hardware description languages
chiggs/md5cracker
A Hardware MD5 Cracker for the Cyclone V SoC
chiggs/oc_jpegencode
Fork of OpenCores jpegencode with Cocotb testbench
chiggs/iverilog
Icarus Verilog
chiggs/support_tickets
Cut-down testcases for various EDA vendor support tickets
chiggs/hidden_wires
Proof-of-concept: Use static variables inside SystemVerilog functions to communicate between modules
chiggs/mdx_wavedrom
Python Markdown extension for inserting wavedrom waveform diagrams into markdown output
chiggs/home
Scripts and settings from my home area