cfelton/pyFDA
Python Filter Design Analysis Tool
Discovered public repositories for cfelton in the GitHub catalog.
Python Filter Design Analysis Tool
Parallella elink DV and alternate implmentation.
MyHDL exercises.
Public repository.
Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.
This is a simple "musicbox" FPGA (HDL) example inspired by a reddit question.
This is a myhdl test environment for the open-cores jpeg_encoder.
This is a myhdl test environment for the USRP simple_gemac core.
that FPGA flow
Fuzzy Logic SciKit (Toolkit for SciPy)
Exploration of alternative hardware description languages
Compare HDLs
A collection of HDL cores written in MyHDL.